As it is well known in this specific field of application, one of the Flash memory reliability problems is linked to single bits shifting from the original threshold value as a consequence of the stresses they undergo during the memory device operating life.
For example, a memory cell being programmed at the logic value “0” and having a predetermined threshold can shift to a lower threshold after undergoing a stress during the programming phase.
In general, if a bit value has shifted to a lower threshold after undergoing a programming stress can be reprogrammed selectively and brought back to the initial threshold value, it is not so easy to bring a bit back to a lower threshold if the bit has previously moved toward higher threshold values. At present, the prior art provides no solutions allowing the erased bits whose threshold has increased and has been detected by an erase-verify phase to be selectively brought back within a distribution of values “1”.
This shift to higher threshold values can occur for example during a reading disturb in electric programming and erasing flash memories.
This phenomenon has been noticed also in cells having undergone a programming drain stress in page/sector-programmed flash memories. Cell matrices of this kind are described for example in the U.S. Pat. No. 6,133,604.
The technical problem underlying the present invention is to provide an erasing method, having such characteristics as to reduce selectively the threshold value of memory cells whose threshold has increased, with respect to the original value, as a consequence of stress or disturbs occurred during their use. This would make the lifetime of memory devices incorporating cells which may be affected by this problem longer.